Overview of Physical Design Engineers

4:22 AM Rajesh singh 3 Comments

Physical design is a very important step which comes right after the circuit design in a standard design cycle. Currently, the circuit representations of the components of the major design are being transformed into a geometric representation of shapes. These geometric shapes are later on manufactures into layers of materials which will make sure that the components are serving their main purpose. This entire geometric representation of shapes is called an IC layout. In this physical design step, a multiple sub-steps are also involved which comprises both the design and verification of the layout.

Each of the steps involved has a particular design flow to follow. The flow of physical design consumes all the technology library which are provided by the fabrication houses. The technology library consists of the files which give information about the type of standard cells used, the type of silicon wafer used and the layout rules that were followed. The physical design of the Integrated Circuit can be categorized into two halves by the physical design engineer.

The two major types of IC design are:

a) Full Custom: In this type, the designer has the complete independence and flexibility over the layout design. For the full customised design type, he needs no predefined cells.

b) Semi-Custom: The designer in this design has partial flexibility. Here, he has to use all the pre-designed cells which are tested with DFM but he has complete independence in figuring out where to place them and how to route them.
The major steps which a designer follows to develop the design follow are as follows:

1. Design Netlist (create right after synthesis)
2. Floor Planning
3. Partitioning
4. Placement
5. Clock-tree Synthesis (CTS)
6. Routing
7. Physical Verification
8. GDS II Generation
1. Designer Netlist: The major information stored on the netlist are types of cells used and their entire interconnectivity process. Once the design meets the purpose of functionality, the netlist is further sent ahead for planning the physical design flow.

2. Floor Planning: This is the first step where an engineer figures out the structures that can be placed close to one another and how to allocate space for them in times of conflict. It takes into account all the routing possibilities, IO structure, other IP cores and macros of the design.

3. Partitioning: Here the chip gets divided into small blocks to ease out the routing and placement. The technique of logical partitioning can also be used.

4. Placement: Carried out in four optimization phases, it can calculate downsize of cells and move the cell or bypass and split it if required. It also redoes HFN synthesis.

5. Clock Tree Synthesis: The major aim of CTS is to reduce skew and the insertion delay. Two types of pins are utilised for CTS- ignore pins and sync pins.

6. Routing: It maintains the actual connection by allocating resources. Routing also tracks assignment required for a specific net.

7. Physical Verification: It checks the authenticity of the entire compiled layout design.

Suppose you are planning to set up an industry in Bangalore, then you can look for physical design engineer Bangalore and get an idea about chip designs, block-level custom layouts and time budgeting which will benefit you.


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